Digital ASIC Designer - European Organization for Nuclear Research (Geneva)

About this position

The summary below is published by European Organization for Nuclear Research on the official vacancy notice. Our own analysis — salary realism, comparable openings, career trajectory, language profile — follows further down the page.

Key responsibilities

According to the vacancy notice, the role centres on the following duties:

• Analyse application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC
• Contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology
• Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core
• Design, integrate, and validate peripheral IP blocks within the CERN SOCRATES framework
• Apply fault-tolerant design methodologies, including triple modular redundancy (TMR) and single-event upset (SEU) mitigation techniques
• Participate in design verification activities and physical implementation, from RTL development through to tapeout
• Contribute to post-silicon testing, characterisation, and validation following chip fabrication

Are you eligible?

Check these requirements from the notice before investing time in an application:

• Education: Master's degree with 2 to 6 years of post-graduation professional experience, or PhD with no more than 3 years of post-graduation professional experience
• Experience: Professional background in Electronics Engineer (or a related field)
• Languages: English (spoken…), French
• Key skills: RTL design and simulation (Verilog / SystemVerilog), Digital ASIC design flow, including synthesis, place-and-route, timing closure, and sign-off activities, Knowledge of RISC-V architecture and its ecosystem, Microcontroller embedded systems development (firmware in C, peripheral interfacing, bare-metal programming), Scripting and automation (Python or equivalent), Linux/Unix working environment, Fault-tolerant design techniques and radiation effects in CMOS circuits, Ability to work independently as well as within a team
• Eligibility: You are a national of a CERN Member or Associate Member State. You have never had a CERN fellow or graduate contract before.

Contract and working arrangements

Contract duration: 24 months, with a possible extension up to 36 months maximum.

Working arrangements: Fully Onsite.

Hiring unit: EP-ESE-ME.

Position details

Reference

EP-ESE-ME-2026-134-GRAP

Last Verified

27 August 2026

Position overview

This is the official EU Careers listing for Digital ASIC Designer at CERN based in Geneva (Other). The vacancy reference is EP-ESE-ME-2026-134-GRAP. The role falls under the Research domain.

Join CERN's EP-ESE-ME section in the development of a radiation-tolerant microcontroller ASIC for use in future particle physics detectors and accelerator systems. Operating in highly challenging radiation environments, these systems require robust and reliable embedded electronics.

The project is based on an open-source RISC-V processing core and the CERN SOCRATES (System-On-Chip Radiation-Tolerant Ecosystem) framework for fault-tolerant SoC design. The successful candidate will contribute to the full development cycle, from requirements definition and system architecture to implementation, verification, and post-silicon validation.

Your responsibilities:

- Analyse application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC. - Contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology. - Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core. - Design, integrate, and validate peripheral IP blocks within the CERN SOCRATES framework. - Apply fault-tolerant design methodologies, including triple modular redundancy (TMR) and single-event upset (SEU) mitigation techniques. - Participate in design verification activities and physical implementation, from RTL development through to tapeout. - Contribute to post-silicon testing, characterisation, and validation following chip fabrication.

Your profile:

- Strong understanding of digital logic design. - Solid experience with digital IC design and RTL development (Verilog/SystemVerilog). - Familiarity with standard ASIC design flows (synthesis, place and route, timing closure). - Knowledge of RISC-V architecture and its ecosystem. - Experience with microcontroller-based embedded systems development, including firmware programming in C and peripheral interfacing.

Skills:

- RTL design and simulation (Verilog / SystemVerilog). - Familiarity with the digital ASIC design flow, including synthesis, place-and-route, timing closure, and sign-off activities. - Knowledge of fault-tolerant design techniques and radiation effects in CMOS circuits is an asset. - Microcontroller embedded systems development (firmware in C, peripheral interfacing, bare-metal programming). - Scripting and automation (Python or equivalent). - Linux/Unix working environment. - Curiosity and willingness to learn in a multidisciplinary environment. - Ability to work independently as well as within a team. - Spoken and written English, with a commitment to learn French.

Eligibility criteria:

- You are a national of a CERN Member or Associate Member State. - You have a professional background in Electronics Engineer (or a related field) and have either: - a Master's degree with 2 to 6 years of post-graduation professional experience; - or a PhD with no more than 3 years of post-graduation professional experience.

- You have never had a CERN fellow or graduate contract before.

Job closing date:02.09.2026 at 23:59 CEST.

Contract duration: 24 months, with a possible extension up to 36 months maximum.

Working hours: 40 hours per week

Job flexibility: Fully Onsite

Target start date: 01-October-2026

Job reference: EP-ESE-ME-2026-134-GRAP

Field of work: Electrical or Electronics Engineering

Benchmark job: 200050 - Electronics Engineer

Global Benefits

- A monthly stipend between 6372-7004 Swiss Francs per month (tax free) depending on your degree. - 30 days of paid leave per year plus 2 weeks annual closure. - Coverage by CERN’s comprehensive health insurance scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund. - Family, child and infant monthly allowances depending on your individual circumstances. - A relocation package (installation grant and travel expenses) depending on your individual circumstances. - Possibility to extend your contract up to 36 months. - On-the-job and formal training including language classes.

Overview of CERN -Discover a world where the impossible is made possible!

At CERN, the European Organization for Nuclear Research, we are pushing the frontiers of science and technology. Our groundbreaking work brings together not only physicists but also a diverse range of professionals from engineering, technical, scientific, and administrative fields. Together, we foster an environment where innovation and collaboration thrive.

Every day, we face exciting new challenges and opportunities to contribute to cutting-edge research that shapes our understanding of the universe. We meet these challenges through the diverse perspectives within our teams, ensuring every contribution is valued and driving our shared sense of inclusion and purpose. Diversity is a core value of CERN since its foundation, and it remains central to our mission and continued success.

If you are ready to be part of a dynamic, inclusive community pushing the boundaries of knowledge, CERN is the place where your curiosity and skills can thrive. Be part of our mission to uncover what lies at the heart of the universe!TAKE PART!

More information about us, here:careers.cern

Application timeline

This vacancy was first listed on 12 August 2026, 16 days ago.

No closing date is published in the source feed for this position. EU vacancies typically remain open for four to eight weeks; check the official vacancy notice for the cut-off date and time.

Last verified against the EU Careers feed on 27 August 2026.

Where to learn more

For headcount, mission, and other open vacancies at CERN see the CERN institution page; for the cost of living, correction coefficient, and other postings in Geneva see our Geneva location page; for related vacancies in the Research field browse our Research domain page.

New to EU careers? Our beginner's guide walks through entry routes, EPSO competitions, and what to prepare. For application logistics see application tips and EPSO competitions.